Integrated circuits, or ICs, are created by patterning a substrate and materials deposited on the substrate. The substrate is typically a semiconductor wafer. The patterned features make up devices and interconnections. This process generally starts with a designer creating an integrated circuit by hierarchically defining functional components of the circuit using a hardware description language. From this high-level functional description, a physical circuit implementation dataset is created, which is usually in the form of a netlist. This netlist identifies logic cell instances from a cell library, and describes cell-to-cell connectivity.
A layout file is then created using the netlist. This is accomplished through a placing and routing process, which assigns logic cells to physical locations in the device layout and routes their interconnections. The physical layout is typically described as many patterned layers, and the pattern of each layer is described by the union of a set of polygons. The layout data set is stored, for example in GDSII (“Graphic Data System II”) or OASIS (“Open Artwork System Interchange Standard”) formats. Component devices and interconnections of the integrated circuit are constructed layer by layer. A layer is deposited on the wafer and then it is patterned using a photolithography process and an etch process. One or more photomasks are created from the layout file for the photolithography of each layer. Photomasks are used to transfer the layout pattern onto the physical layer on the wafer. A photomask, or mask, provides an image of the desired physical geometries of the respective integrated circuit layer. Passing light through the mask projects the layout pattern for the layer onto the wafer. An imaging lens system projects and focuses the layout onto the substrate. The projected light pattern interacts with a photosensitive resist coating on the wafer and, resist portions that are exposed to light are rendered either soluble or insoluble in a developer solution, depending on the type of the photoresist. Accordingly, the mask pattern is transferred into the photo-resist by optical projection and chemical reactions. The photo-resist pattern is subsequently transferred to an underlying layer by an etch process. Most commonly, plasma containing chemically-selective reactive ions is used to etch high-aspect ratio trenches and holes with close to vertical sidewalls.
With a continuing desire to provide greater functionality in smaller packages and the evolution of system-on-chip and mixed-signal designs, IC feature geometries are being driven to smaller and smaller dimensions. However, the ability to project an accurate image of increasingly smaller features onto the wafer is limited by the wavelength of the light used, and the ability of the lens system. The minimum feature size that a projection system can print can be expressed by:
  CD  =            k      1        ⁢                  λ        NA            .      where CD, critical dimension, is the minimum feature size; k1 is a dimensionless coefficient of process-related factors; λ is the wavelength of light used; and NA is the numerical aperture of the projection lens as seen from the wafer. The equation above is not a black-and-white absolute limit. The yield of the lithographic process gradually decreases, and its cost increases, as k1 decreases below 0.35. Reducing k1 below 0.28 for a single exposure is not practical. There is a fundamental, hard limit for the pitch of a periodic pattern:
  Period  ≥      0.5    ⁢          λ      NA      The pitch limit cannot be violated, irrespective of the photomask and resolution enhancement technologies that may be used, when using a resist employing a single-photon reaction. The reason for this limitation is that the optical intensity image produced inside the photo-resist is band-limited in the spatial-angular-frequency domain. When the intensity image is Fourier transformed with respect to the x and y coordinates (coordinates in the plane of the wafer), the support of the transformed intensity image is contained in a disk of radius 4πNA/λ. Patterns that can be printed by a single lithography step are approximately level curves of such band-limited functions.
Presently, the most advanced high-volume lithography technology uses 193 nm wavelength Argon fluoride (ArF) excimer laser as a light source and a projection lens with 1.35 numerical aperture, which cannot print pitches smaller than 67 nm in a single lithography step. Accordingly, the resolution limit of conventional lithography technology is increasingly being challenged by the shrinking dimensions of critical IC feature geometries.
Double Patterning: One class of technologies used to enhance feature density is referred to as double patterning or multiple patterning. There are several types of double patterning in use, the most common being: litho-etch-litho-etch (LELE); litho-freeze-litho-etch (LFLE); self-aligned double patterning (SADP), also known as spacer-assisted double patterning, or sidewall image transfer (SIT).
Litho-etch-litho-etch process and the Litho-Freeze-Litho-etch process decompose the layout into two parts, each of which is approximately the level curve of a properly band-limited intensity image. The decomposition is similar to coloring a geographical map using two colors such that no two neighboring countries have the same color. By analogy, the decomposition of the layout into two parts can be called “coloring the layout.” Features that are assigned the first “color” are printed by a first lithography step, and features that are assigned the second color are placed printed by a second lithography step. In this terminology, color is merely an index, not a physical color.
Trench-decomposition variant of Litho-Etch-Litho-Etch: According to the trench-decomposition variant of LELE, the pattern is expressed as the union of two sets of trenches. The trench-decomposition LELE method is topologically suitable for double patterning damascene metal layers. Now referring to FIGS. 1a-d, the first set of trenches 1 is etched into a hardmask 2 by using a first lithography step and a first etch step (FIG. 1a) and an anti-reflective coating 4 and a second photo-resist 5 are spun on the hardmask (FIG. 1b). The second set of trenches 7 are etched into the hardmask 2 by a second lithography step (FIG. 1c), and a second etch step is performed (FIG. 1d). The union of the two set of trenches 1 and 7 in the hardmask 2 are transferred into an underlying layer by a third etch process (not shown). A hardmask is usually a film deposited on top of the layer to be patterned. The hardmask and the layer to be patterned are chemically distinct so that they can be selectively etched, one at a time.
SADP (SIT) method is a known method of double patterning [C. Bencher, “SADP: The Best Option for 32 nm NAND Flash,” Nanochip Technology Journal, Issue 2, 2007]. Referring to FIGS. 2a-c, in the SADP method, a core (also called mandrel) pattern 10 is formed on a wafer by a lithography and an etch process (FIG. 2a). The core pattern 10 is formed over a dielectric layer 15 which is deposited on a wafer 20. A spacer material 25, for example Si3N4, is deposited on the core pattern (FIG. 2b). The spacer material is etched by a plasma process in a way that etches horizontal surfaces faster. FIG. 2c shows the cross-section of the wafer after the spacer-etch process. Sidewalls of features (islands) in the core pattern 10 are covered by spacers 35.
Wire-by-trench variant of SADP: In wire-by-trench SADP process, the spacer pattern defines the dielectric between metal connections. Core pattern 10 is removed by a chemically selective etch process, leaving behind sidewall spacers 35 (FIG. 2d-1). The sidewall spacer pattern is transferred to the dielectric layer 15 using an etch process (FIG. 2e-1). There may be one or more hardmask layers between the spacers 35 and the dielectric layer 15. In that case, the spacer pattern is transferred into the dielectric layer 15 using multiple etch processes. Trenches are formed in the dielectric layer. Via holes (not shown) are etched at this step in the dual damascene process. Trenches and vias holes are filled by metal. In the damascene process, trenches are coated by barrier and seed layers, and copper is electro-deposited into the trenches and vias. Excess copper is removed by a CMP (chemical-mechanical planarization) leaving copper 40 only in the trenches and vias (FIG. 2f-1).
Wire-by-Spacer Variant of SADP: In wire-by-spacer SADP process, the spacer pattern defines the metal interconnection pattern. The conceptually simplest way of achieving this would be to make the spacers out of metal. This is not practiced because there is not a good etch process for copper, which is the interconnection metal preferred for its high conductance. Wire-by-trench method follows the steps of FIG. 2a-c. Then, the spacers are covered by the core material 50, or a chemically similar material, as shown in FIG. 2d-2. This deposition fills the spaces between the spacers 35. The spacers and core material are thinned by CMP (FIG. 2e-2) to make the cross-section of the spacers more rectangular. The spacers are removed by a chemically selective etching process (FIG. 2f-2). Where the spacers 35 were, are now trenches 36. The trench pattern is transferred by an etch process to the dielectric layer that will support the wires (FIG. 2g-2). Via holes (not shown) are etched at this step according to the dual damascene process, using a separate lithography and etch step. Trenches in the dielectric layer 37 and via holes are filled with metal. Finally, metal 37 is in the position of the spacers, and dielectric is in the position of the core 51 and spaces between spacers 52.
Limitations of Double Patterning: LELE Double patterning cannot print a set of odd number of features when each feature is at a minimum critical distance from another feature in the set. Such sets of features can be called odd cycles or color conflicts. Odd cycles can be arbitrarily large both in physical extent and in number of features. Presence of odd cycles cannot be checked by a local operation. In this case, “local” means limited to a neighborhood of the wafer (x-y) plane, such that the diameter of the neighborhood is less than several times (e.g., 5 times) the minimum feature dimension. Similarly, if an odd cycle is detected, it cannot necessarily be repaired by a local operation without creating another odd cycle. Prior art double patterning teaches resolving a color conflict by breaking up a feature into overlapping pieces, and coloring the pieces in different colors. For example, breaking one of the features into two in an odd cycle makes even number of features. However, the new coloring scheme can produce a new color conflict. If a layout is created disregarding limitations of double patterning, a valid decomposition may not be achieved within an acceptable time or amount of computation.
Damascene Process: Damascene process is used to make copper interconnections in integrated circuits. In the damascene process, interconnections are etched as trenches into a dielectric layer, such as SiO2 or TEOS. The trenches are lined with a thin film of a diffusion barrier such as titanium nitride or tantalum nitride. The barrier film prevents metal atoms from diffusing into the dielectric. Trenches are then lined with a thin film of conductive layer that seeds electro-deposition. The barrier and seed layers are typically deposited by a physical or chemical vapor deposition. The trenches are filled with a metal, typically copper, by a wet electro-deposition process. Electro-deposition not only fills the trenches but coats the wafer with an excess layer of metal. Excess metal is removed by chemical-mechanical planarization, which leaves metal only in trenches and vias. Metal trenches (wires) at different layers are connected by vertical interconnections called vias. Vias are made by etching holes in a dielectric layer and filling the holes with metal. Dual damascene process etches a layer of trenches and a layer of via holes (also called via cuts), in two separate lithography steps. Vias are etched deeper than the trenches, down to the previous metal layer. There is a trench-first dual damascene process and a via-first dual damascene process. In either variant of the dual damascene process, via holes and trenches are metal filled in one set of barrier, seed, and metal depositions. Conventionally, the trench layer is patterned with a single lithography step, and associated via holes are patterned with another single lithography step. Manufacturing of logic devices below the 22 nm node may require double patterning of either or both of the trench layer and the via hole layer.
Single-cut and double-cut vias: Some wires on adjacent routing layers are connected by vias. Vias can be single-cut or double-cut. A single-cut is usually drawn as a square, but reproduces having approximately a circular cross-section in the x-y plane due to the limited resolution of lithography. In three dimensions, a single cut via is approximately a circular cylinder. The diameter of a single-cut via is comparable to the width of a wire (trench). Single-cut vias have some probability of being either open circuit or having an unacceptably high resistance due to variations in lithography, etch, and deposition processes. Double-cut vias are used to lower the probability of having poorly connected vias. A double-cut via is either two adjacent vias connected in parallel, or preferably one via that is drawn having a rectangular cross-section, which is rendered as an oblong cross-section by lithography. The long dimension of a rectangular double-cut via is two times the wire width or greater, and its short dimension is comparable to the wire width. Where wires in adjacent layers have alternating preferred directions, a double-cut via necessarily has its long direction perpendicular to the preferred direction of one of the two layers it connects.